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| SN54/74LS166 8-BIT SHIFT REGISTERS The SN54L/ 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/ 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. 8-BIT SHIFT REGISTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 * Synchronous Load * Direct Overriding Clear * Parallel to Serial Conversion PARALLEL PARALLEL INPUTS F 11 F E 10 E CLEAR 9 16 1 N SUFFIX PLASTIC CASE 648-08 SHIFT/ INPUT OUTPUT H QH G VCC LOAD 16 15 14 13 12 SHIFT/ LOAD H QH G 16 1 D SUFFIX SOIC CASE 751B-03 SERIAL INPUT A 1 SERIAL INPUT 2 A B 3 B C 4 C D 5 D CLEAR CLOCK INHIBIT CK 8 6 7 CLOCK CLOCK GND INHIBIT ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC PARALLEL INPUTS FUNCTION TABLE INPUTS CLEAR L H H H H H SHIFT/ LOAD X X L H H X CLOCK INHIBIT X L L L L H PARALLEL CLOCK X L SERIAL A...H X X X H L X X X a...h X X X QA L QA0 a H L QA0 QB L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 INTERNAL OUTPUTS OUTPUT QH FAST AND LS TTL DATA 5-1 SN54/74LS166 Typical Clear, Shift, Load, Inhibit, and Shift Sequences CLOCK CLOCK INIHIBIT CLEAR SERIAL INPUT SHIFT/LOAD A B C PARALLEL INPUTS D E F G H OUTPUT QH SERIAL SHIFT CLEAR (9) CLEAR (1) SERIAL INPUT (15) SHIFT/LOAD (2) A R CK S H L H L H L H H INHIBIT LOAD HH L HLHL SERIAL SHIFT H QA B (3) R S CK QB C (4) R S CK QC D (5) R S CK E (10) R QD CK S F (11) R QE CK S QF (12) G R CK S QG H CLOCK CLOCK INHIBIT (14) (7) (6) R S CK (13) Q H FAST AND LS TTL DATA 5-2 SN54/74LS166 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 38 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-3 SN54/74LS166 TEST TABLE FOR SYNCHRONOUS INPUTS DATA INPUT FOR TEST H Serial Input SHIFT/LOAD 0V 4.5 V OUTPUT TESTED QH at tn+1 QH at tn+8 AC WAVEFORMS tw(clear) CLEAR INPUT Vref Vref 0V tn CLOCK INPUT Vref tw(clock) DATA INPUT (SEE TEST TABLE) Vref Vref tsu tn + 1 (SEE NOTE 1) tn tn + 1 3V Vref th Vref tsu Vref th Vref 0V tPHL (clear-Q) Vref tPHL (CLK-Q) VOH Vref Vref VOL NOTE 1. tn = bit time before clocking transition NOTE 1. tn+1 = bit time after one clocking transition NOTE 1. tn+8 = bit time after eight clocking transition NOTE 1. LS166 Vref = 1.3 V. 3V 0V 3V tPLH (CLK-Q) OUTPUT Q AC CHARACTERISTICS (TA = 25C) Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Clock Frequency Clear to Output Clock to Output Min 25 Typ 35 19 23 24 30 35 35 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol tW ts ts th Parameter Clock Clear Pulse Width Mode Control Setup Time Data Setup Time Hold Time, Any Input Min 30 30 20 15 Typ Max Unit ns ns ns ns VCC = 5.0 V Test Conditions FAST AND LS TTL DATA 5-4 |
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